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111 Bewertungen

Über den Kurs

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

Top-Bewertungen

JS
6. Juni 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

KK
4. Juni 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .

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76 - 100 von 112 Bewertungen für Hardware Description Languages for FPGA Design

von KUNAL M

17. Mai 2020

Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.

von Timothy A

30. Apr. 2020

I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.

von MANISH K S

16. Mai 2020

This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.

von Rohit l

2. Mai 2020

The Verilog course was very good.

However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.

von Michael W B

23. Juni 2021

Good VHDL intro, Verilog was kind of light, especially the reference material. Free Range VHDL was a great reference. The Verilog section needs something similar.

von harsh

15. Mai 2020

The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

von Rishi J

4. Sep. 2020

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.

von Aishwarya S

7. Mai 2020

FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.

von Julio T A

2. Apr. 2021

Siento que faltan mas ejemplos y practicas, y en cuanto al apartado de lenguaje Verilog falta explicar aun mas sintaxis

von Raghul R

25. Juni 2020

Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.

von KUNAPAREDDY S N

14. Mai 2020

this course is given good idea of Hardware Description Language and i understood the concepts well.

von Muhammad Z Y

7. Apr. 2020

Course content is moderate. But also have complexity level higher for a beginner.

von Uzair A

9. Okt. 2020

its a very nice course. Its help me a lot to understand the basic of fpga.

von Apoorva S

25. Mai 2020

A very engaging course to do for beginners having fundamentals strong.

von Yuvraj S R

18. Mai 2020

Explanations are not that good for some circuits like memory

von Sourav N

18. Sep. 2020

There should have been more examples of problems.

von MOHAMED C

30. Apr. 2020

a big thank you to all the professiors

von Prakash K R

24. Juni 2020

It should be more elaborative

von TUMMALAPALLI S V N S

7. Juni 2020

BEST FOR THE BASIC

von J S

5. Aug. 2020

good

von Hanming Z

18. Apr. 2021

The course lectures are useful and explanatory. The reason why I deduct 2 stars is homework instructions are sometimes very vague, e.g. synchronous reset or not, instruction's variable name does not match the ones given in starter code. The homework starter code sometimes contain errors too. The makes writing the homework sometimes a guess work of whether the code should be implemented one way vs. another.

von Islam E

31. Mai 2020

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

von V S V

29. Sep. 2020

Videos could be better, felt it was too fast and didn't cover the concepts well enough

von Harsh A

15. Juni 2020

Verilog part is explained very well but VHDL part completely unsatisfied.

von Sachin A

21. Apr. 2020

Very introductory. Verilog and VHDL exercises are copied.