Kursteilnehmer-Bewertung und -Feedback für Hardware Description Languages for FPGA Design von University of Colorado Boulder
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I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .
This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .
76 - 100 von 112 Bewertungen für Hardware Description Languages for FPGA Design
von KUNAL M
•Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.
von Timothy A
•I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.
von MANISH K S
•This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
von Rohit l
•The Verilog course was very good.
However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.
von Michael W B
•Good VHDL intro, Verilog was kind of light, especially the reference material. Free Range VHDL was a great reference. The Verilog section needs something similar.
von harsh
•The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.
von Rishi J
•The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.
von Aishwarya S
•FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.
von Julio T A
•Siento que faltan mas ejemplos y practicas, y en cuanto al apartado de lenguaje Verilog falta explicar aun mas sintaxis
von Raghul R
•Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.
von KUNAPAREDDY S N
•this course is given good idea of Hardware Description Language and i understood the concepts well.
von Muhammad Z Y
•Course content is moderate. But also have complexity level higher for a beginner.
von Uzair A
•its a very nice course. Its help me a lot to understand the basic of fpga.
von Apoorva S
•A very engaging course to do for beginners having fundamentals strong.
von Yuvraj S R
•Explanations are not that good for some circuits like memory
von Sourav N
•There should have been more examples of problems.
von MOHAMED C
•a big thank you to all the professiors
von Prakash K R
•It should be more elaborative
von TUMMALAPALLI S V N S
•BEST FOR THE BASIC
von J S
•good
von Hanming Z
•The course lectures are useful and explanatory. The reason why I deduct 2 stars is homework instructions are sometimes very vague, e.g. synchronous reset or not, instruction's variable name does not match the ones given in starter code. The homework starter code sometimes contain errors too. The makes writing the homework sometimes a guess work of whether the code should be implemented one way vs. another.
von Islam E
•this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it
von V S V
•Videos could be better, felt it was too fast and didn't cover the concepts well enough
von Harsh A
•Verilog part is explained very well but VHDL part completely unsatisfied.
von Sachin A
•Very introductory. Verilog and VHDL exercises are copied.
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