This course will introduce you to all aspects of development of Soft Processors and Intellectual Property (IP) in FPGA design. You will learn the extent of Soft Processor types and capabilities, how to make your own Soft Processor in and FPGA, including how to design the hardware and the software for a Soft Processor. You will learn how to add IP blocks and custom instructions to your Soft Processor. After the Soft Processor is made, you learn how to verify the design using simulation and an internal logic analyzer. Once complete you will know how to create and use Soft Processors and IP, a very useful skill.
Dieser Kurs ist Teil der Spezialisierung Spezialisierung FPGA Design for Embedded Systems
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Spezialisierung FPGA Design for Embedded SystemsUniversity of Colorado BoulderÃœber diesen Kurs
8.886 kürzliche Aufrufe
Flexible Fristen
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Zertifikat zur Vorlage
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Beginnen Sie sofort und lernen Sie in Ihrem eigenen Tempo.
Kurs 3 von 4 in
Stufe „Mittel“
Practicing engineer or graduate level engineering student.
Ca. 10 Stunden zum Abschließen
Englisch
Untertitel: Arabischer Raum, Französisch, Portugiesisch (europäisch), Italienisch, Vietnamesisch, Deutsch, Russisch, Englisch, Spanisch
Was Sie lernen werden
Create a Nios II softcore processor hardware design using the Altera development flow
List the types of IP available for FPGAs
Use simulation with ModelSim to verify an FPGA Design
Kompetenzen, die Sie erwerben
- Software Design for Softcore Processors
- Softcore Processor Design
- Programmable Logic Design
- Simulation for Verification
- Intellectual Property Integration
Flexible Fristen
Setzen Sie Fristen gemäß Ihrem Zeitplan zurück.
Zertifikat zur Vorlage
Erhalten Sie nach Abschluss ein Zertifikat
100Â % online
Beginnen Sie sofort und lernen Sie in Ihrem eigenen Tempo.
Kurs 3 von 4 in
Stufe „Mittel“
Practicing engineer or graduate level engineering student.
Ca. 10 Stunden zum Abschließen
Englisch
Untertitel: Arabischer Raum, Französisch, Portugiesisch (europäisch), Italienisch, Vietnamesisch, Deutsch, Russisch, Englisch, Spanisch
von
University of Colorado Boulder
CU-Boulder is a dynamic community of scholars and learners on one of the most spectacular college campuses in the country. As one of 34 U.S. public institutions in the prestigious Association of American Universities (AAU), we have a proud tradition of academic excellence, with five Nobel laureates and more than 50 members of prestigious academic academies.
Beginnen Sie damit, auf Ihren Master-Abschluss hinzuarbeiten.
Dieses Kurs ist Teil des reinen Onlineabschlusses Master of Science in Electrical Engineering von University of Colorado Boulder.
Wenn Sie in das komplette Programm aufgenommen werden, werden Ihre Kurse auf Ihren Abschluss angerechnet.
Lehrplan - Was Sie in diesem Kurs lernen werden
2 Stunden zum Abschließen
Softcore Processor Development Flow
This module introduces the concept of a soft processor in general, and of hardware design for the soft processor in particular. It presents an overview of soft processors, describing all the different kinds that are available from Xilinx, Altera, Microsemi, and Lattice and then goes into depth about the Nios II soft processor from Altera. The benefits of using soft processors to prevent obsolescence and provide flexibility are explained. The content guides you through a hardware design of the Nios II processor using Qsys, the Altera system design tool. Lastly, design of a custom instruction in the Nios II is presented, showing the versatility of the soft processor in an FPGA.
2 Stunden zum Abschließen
11 Videos (Gesamt 86 min), 1 Lektüre, 1 Quiz
3 Stunden zum Abschließen
Writing Software for Softcore Processors
This module delves further into the development of soft processors, It describes the soft processor development flow in more detail, including the tools needed to develop software for the soft processor. It then introduces the Eclipse-based IDE for Nios II software development, and then shows how the output of the Qsys design is used to establish a Board Support Package (BSP) for the processor, which is necessary because the processor hardware design can be changed and the BSP software library must support any changes. Use of the BSP editor to configure the processor by programming control registers is demonstrated. Finally, the use of the custom instruction developed in Module 1 is presented, including the use of software macros to complete the implementation of the custom instruction.
3 Stunden zum Abschließen
8 Videos (Gesamt 33 min), 1 Lektüre, 1 Quiz
2 Stunden zum Abschließen
IP Acquisition and Integration
Modern FPGA design is no longer centered on HDL module design as it is on acquisition and use of IP Cores. In this Module we will introduce IP cores including offerings from all the major vendors, Intel Altera, Xilinx, Microchip Microsemi, and Lattice. You will learn how to find, acquire, and use these cores.
2 Stunden zum Abschließen
6 Videos (Gesamt 26 min), 1 Lektüre, 1 Quiz
4 Stunden zum Abschließen
Introducing ModelSim and Simulation for Verification
As we work on more complex FPGA designs, the challenges to create an error-free design mount exponentially. Having a good grasp of the tools needed to verify correctness of design has become more and more important. After introducing simulation in previous sessions, in this module we will examine simulation with ModelSim in more depth by working through some examples. This will show the utility of simulation for verification and debugging. This module will also describe in some detail how the simulator works and how it achieves concurrency through the use of delta delays. As a final step in the debugging process, the internal logic analyzer SignalTap II is introduced.
4 Stunden zum Abschließen
8 Videos (Gesamt 67 min), 1 Lektüre, 1 Quiz
Bewertungen
- 5 stars50Â %
- 4 stars16,07Â %
- 3 stars25Â %
- 2 stars5,35Â %
- 1 star3,57Â %
Top-Bewertungen von FPGA SOFTCORE PROCESSORS AND IP ACQUISITION
von BT11. Juni 2021
Must-take Course for Hardware Engineeer. This course provides new concept about NIOS II 32-bit RISC Architecture and How HDL Simulation work
von HS7. Sep. 2021
The course bring good theoric bases to IPCores but leaves short informacion about the Qsys use, memory map and others things that are necesary for system integration.
von MB11. Aug. 2021
I was hoping to get more lecture material on writing testbench code.
von OS8. Dez. 2020
I feel I did another small step towards mastering designing with fpga. Thank you!
Ãœber den Spezialisierung FPGA Design for Embedded Systems
The objective of this course is to acquire proficiency with Field Programmable Gate Arrays (FPGA)s for the purpose of creating prototypes or products for a variety of applications. Although FPGA design can be a complex topic, we will introduce it so that, with a little bit of effort, the basic concepts will be easily learned, while also providing a challenge for the more experienced designer. We will explore complexities, capabilities and trends of Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD). Conception, design, implementation, and debugging skills will be practiced. We will learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP. Projects will involve the latest software and FPGA development tools and hardware platforms to help develop a broad perspective of the capabilities of various Programmable SoC solutions. Topics include:
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