Über diesen Kurs
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Stufe „Mittel“

Ca. 12 Stunden zum Abschließen

Englisch

Untertitel: Englisch

100 % online

Beginnen Sie sofort und lernen Sie in Ihrem eigenen Tempo.

Flexible Fristen

Setzen Sie Fristen gemäß Ihrem Zeitplan zurück.

Stufe „Mittel“

Ca. 12 Stunden zum Abschließen

Englisch

Untertitel: Englisch

Lehrplan - Was Sie in diesem Kurs lernen werden

Woche
1
1 Stunde zum Abschließen

Orientation

In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course.

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2 Videos (Gesamt 23 min), 2 Lektüren, 1 Quiz
2 Videos
Two Tools Tutorial4m
2 Lektüren
Syllabus10m
Tools For This Course10m
1 praktische Übung
Demographics Survey5m
3 Stunden zum Abschließen

ASIC Placement

In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks.

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9 Videos (Gesamt 163 min), 2 Lektüren
9 Videos
Wirelength Estimation15m
Simple Iterative Improvement Placement12m
Iterative Improvement with Hill Climbing15m
Simulated Annealing Placement27m
Analytical Placement: Quadratic Wirelength Model14m
Analytical Placement: Quadratic Placement26m
Analytical Placement: Recursive Partitioning18m
Analytical Placement: Recursive Partitioning Example16m
2 Lektüren
Week 1 Overview10m
Week 1 Assignments10m
Woche
2
6 Stunden zum Abschließen

Technology Mapping

Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD.

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6 Videos (Gesamt 102 min), 2 Lektüren, 2 Quiz
6 Videos
Technology Mapping as Tree Covering29m
Technology Mapping—Tree-ifying the Netlist13m
Technology Mapping—Recursive Matching9m
Technology Mapping—Minimum Cost Covering16m
Technology Mapping—Detailed Covering Example14m
2 Lektüren
Week 2 Overview10m
Week 2 Assignments10m
1 praktische Übung
Problem Set #11h
Woche
3
4 Stunden zum Abschließen

ASIC Routing

Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment.

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9 Videos (Gesamt 145 min), 2 Lektüren, 1 Quiz
9 Videos
Maze Routing: 2-Point Nets in 1 Layer16m
Maze Routing: Multi-Point Nets12m
Maze Routing: Multi-Layer Routing12m
Maze Routing: Non-Uniform Grid Costs14m
Implementation Mechanics: How Expansion Works23m
Implementation Mechanics: Data Structures & Constraints18m
Implementation Mechanics: Depth First Search14m
From Detailed Routing to Global Routing15m
2 Lektüren
Week 3 Overview10m
Week 3 Assignments10m
1 praktische Übung
Problem Set #21h
Woche
4
7 Stunden zum Abschließen

Timing Analysis

You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design.

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8 Videos (Gesamt 148 min), 2 Lektüren, 2 Quiz
8 Videos
Logic-Level Timing: Basic Assumptions & Models30m
Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks27m
Logic-Level Timing: A Detailed Example and the Role of Slack10m
Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths26m
Interconnect Timing: Electrical Models of Wire Delay16m
Interconnect Timing: The Elmore Delay Model14m
Interconnect Timing: Elmore Delay Examples14m
2 Lektüren
Week 4 Overview10m
Week 4 Assignments10m
1 praktische Übung
Problem Set #31h
4.8
15 BewertungenChevron Right

Top reviews from VLSI CAD Part II: Layout

von ALOct 21st 2018

Great basic overview of the core design principles for EDA

Dozent

Avatar

Rob A. Rutenbar

Adjunct Professor
Department of Computer Science

Über University of Illinois at Urbana-Champaign

The University of Illinois at Urbana-Champaign is a world leader in research, teaching and public engagement, distinguished by the breadth of its programs, broad academic excellence, and internationally renowned faculty and alumni. Illinois serves the world by creating knowledge, preparing students for lives of impact, and finding solutions to critical societal needs. ...

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