In this video you'll learn the rationale for use of Finite State Machines, how to create finite state machines using Verilog, and their criteria for determining which state encoding formats to use. Finite State machines are a very important part of digital design and software design, too. The state machine concept provides a highly reliable, maintainable and methodical way to design circuits that perform a sequence of operations with great predictability. State machines are always in a known state. Good designers all use FSMs. Ever since are broadly categorized into two types more or melee as shown in the diagram, and more machines the output only depends on the state. Immediately machines the inputs and the state drive the output, the inputs may be asynchronous with a clock. A single machine may only have more type outputs or only melee or both. So let's look at an example of a finite state machine. In this case, it'll provide a desired angle output to a motor, given a control signal which tells it to go counterclockwise or clockwise. The state diagram showing the transitions from state to state as shown, and here it's shown as the state table as well as a state diagram. If the motor starts out at angle 0 and is told to move clockwise, the next angle will be 45 degrees and so on. The desired angle position is 1 output, and is directly equal to the current state. The other output position error is a combinational output using both the state and an input. The current state usually represented by a collection of flip-flops. However, the way in which is represented, the state encoding, can vary greatly. Here are four common state encodings. The state could be represented by a binary value, or by Gray or Johnson codes which change one bit at a time, or by One-Hot encoding in which each flip-flop represents one state, and flip-flops for n states. As the number of states exceeds a certain threshold, the next state logic will be simpler for the One-Hot designs, allowing them to run at a faster clock frequency. Although binary encoded state machines will minimize the number of flip-flops used. So depending on what your objective is, you would choose a different type of state encoding when you're designing your state machine. So let's examine verilog code for a binary encoded version of a state machine. So the encoding can be established by a parameter for different encoding, one only need to change the parameter table. And this case we've got a pyramidal table that creates a binary set of values for each state, in addition to the clock, reset, the move inputs. There's a sensor input that provides the physical angle of the motor. The current state and the next state variables are vectors so they can adopt the angle encoding. The salient part of the state machine is the case statement which describes the next state logic. So here we show the first state at angle 0, and then also the state when you're at angle 45. The remaining states are omitted here just for space reasons, but then we show you the last state at angle 315. Usually the case statement's a standard approach for building state machines as we've kind of shown here. You always want to make sure you have a default state so that any kind of anomalies are taken care of, and so that you don't infer additional latches in the logic of the design. The current state register is created by use of an always block with the rising edge of the clock, and reset the position is set to match the position given by the external sensor. The state machine has both more outputs, which are only dependent on the state, and mainly outputs which are also dependent on the input position. The position input may not be synchronized with the clock, so the synchronization circuit may need to be added. In general the Gray and Johnson encoding may be more robust in response to a bit change due to a fault as each successive angle is represented by only 1 bit change. A bit change in binary coding could cause 180-degree change in position, and this would represent the actual movement of the motor. So in this case a Johnson or Gray encoding might be a better choice. This is the RTL view from Intel tears quartus Prime FPGA tool after implementation of this state machine and I max10 FPGA. Notice only three flip-flops for the current state register are required. The total number of logic cells use is just 17. This is a very efficient sequencer design. Looking at the code one may not have expected such a result with such a small number of circuits in order to implement the state machine and the state diagram that was shown earlier. After implementing the other encodings we can see that binary coding for this small state machine is the most efficient in terms of size and logic resources. Even though One-Hot uses the most resources, the flip-flops are usually part of the logic cell, so the difference doesn't matter as much as it may seem. As the number of states gets larger though, the difference in resources is going to narrow quite a bit. For designs of more than 20 states, One-Hot often provides the best overall performance. In this video you have learned the rationale for the use of finite state machines, how to create finite State machines using verilog, and criteria for determining which state encoding format to use in your state machine.