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Kursteilnehmer-Bewertung und -Feedback für VLSI CAD Part II: Layout von University of Illinois at Urbana-Champaign

104 Bewertungen
18 Bewertungen

Über den Kurs

You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class)....



Jul 30, 2019

Good course content and prof. `s teaching method makes it easy to comprehend quite quickly.


Oct 21, 2018

Great basic overview of the core design principles for EDA

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1 - 17 von 17 Bewertungen für VLSI CAD Part II: Layout

von Robin M

Dec 29, 2018

As a software developer without background in EE I have always wondered how Boolean logic is turned into actual physical hardware, and this course (along with its predecessor "VLSI CAD Part I: Logic") has answered all my questions.

von Navdeep D

Apr 03, 2019


von Ramana r

Apr 07, 2019


von K L N A

Apr 08, 2019


von Aravind

Apr 09, 2019

no comments

von Shresth N

Apr 10, 2019

very nice and challenging

von Shaanvi M

Mar 11, 2019

very helpful, and delivered very well.

von Pankaj M

Aug 16, 2018

Very good to learn algorithms!

von Akash L

Oct 21, 2018

Great basic overview of the core design principles for EDA

von Kanishka S

Jun 30, 2018

Excellent course, very helpful!


Oct 31, 2017


von Arighna D

May 01, 2019


von Divyang T

Jul 07, 2019

A very good course for students who want to have an understanding of Physical Design process in semiconductor industry. I want to thank professor for making this course so informative. A must for people looking to dive deep into Electronics.

von kanishk j

Jul 30, 2019

Good course content and prof. `s teaching method makes it easy to comprehend quite quickly.

von Md. F K

Aug 03, 2019

Another interesting and well-taught course.


Apr 09, 2019


von Mohammad H

Sep 01, 2018

It was a great experience, really great lecturer without exaggerating, but the programming assignment 3 (which is optional) was totally a nightmare, I wrote about 1000 line of code to do both the essential and the extra parts, but not yet.

I hope there was another course for design using HDL like Verilog or System Verilog.