Jun 05, 2020
This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .
Jul 31, 2020
The course helped in showing the different styles of the Verilog and VHDL coding.\n\nUnderstood the advantages of Verilog and VHDL in real life applications
von Phanindra D•
Mar 18, 2020
Great course with in-depth explanations of HDL with Verilog and VHDL
von Orzumamadov G M•
Jul 10, 2020
Thanks to the authors for such an interesting and useful course.
von kasani J g•
May 05, 2020
it is really fun to learn this course you will really enjoy it,
von mandeep s r•
Aug 01, 2020
This is one of the best courses available on coursera.
von Mahendra V•
Jun 06, 2020
Good Learning with structured assignments.
von Himanshu G•
Mar 29, 2020
A Nice Course which required more hardwork
von Soorya K•
May 08, 2020
Assignment programs are very challenging.
von SAMUELJUDE S•
Jul 07, 2020
extremely short crisp and knowledgeable
von Apurba D•
Aug 09, 2020
Liked the programming assignments...
von Patrick M•
Aug 02, 2020
good mix between theory and practice
von Ehtesham A K•
May 19, 2020
Excellent Course for FPGA learners.
von P S•
Aug 06, 2020
Very well explained the concepts.
von Kondapally M R•
Jun 24, 2020
very informative and practical
von Vinayakumar R B•
May 26, 2020
Very good for beginners
von Lalit B•
Mar 04, 2020
feeling satisfactory after successfully completing the course. the instructors were the expert of the topic and explained very well. some of the programming assignments require more clarifications and learning which i found missing in the videos. videos are not enough to complete those assignments.
i am very happy to have this certification and would love to be the part of more learning by the coursera.
von Samer A A•
Jul 07, 2020
The course gives a good overview for the HDL. However, the assignments templates needs to be revised because there were some errors. Also, the requirements sometimes are vague, there is no specific specifications like synchronous/asynchronous signals active high/low clock. But, overall it was good time to revise HDL. I am looking forward to be involved in more advanced courses related to the FPGAs.
von SANGEERTH P•
Jun 29, 2020
The course content was worthier and good. But the assignments and the methodology of assessing the assignments were not rigorous. The questions were not clear and elaborate. Once I uploaded a wrong Verilog code but I got 10/10 for that assignment. I don't know how. The course content was really good. But the method of evaluating the assignment could be made better.
von pedram k•
Apr 21, 2020
A good combination of introduction to VHDL and Verilog. Cover essential topics for design and test implementation. There are rooms to improvement regarding the assignments description. Also, having the test benches encrypted is fine, but better to make it open source for students once they have get enough grades for that specific problem.
von SHIKHAR S•
May 15, 2020
This course provides insights into the world of hardware design. The assignments provided were quite challenging and diverse. The Testbench files were provided on which the code had to be tested and simulation had to be done on ModelSim, provided by MentorGraphics.It was quite an interesting course.
von KUNAL M•
May 17, 2020
Good for beginners.Though the instructors can improve upon how they present the concepts by incorporating few complex examples on both Verilog and VHDL.The assignments questions need to be different for both the languages.
May 01, 2020
I did love how explanations were made and especially the flexibility in the submission of quizzes and assignment. My understanding of VHDL and Verilog have been made batter. The instructors are top notch.
von MANISH K S•
May 16, 2020
This course is very helpful in understanding the basics of hardware description languages and now after doing this course i am very much comfortable in using verilog and vhdl language.
von Rohit P L•
May 02, 2020
The Verilog course was very good.
However the vhdl course could have been better.Needed a bit more clarity on the assignments.The lectures could have used a bit more explanation.
May 15, 2020
The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.
von Aishwarya S•
May 07, 2020
FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.