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Bewertung und Feedback des Lernenden für Hardware Description Languages for FPGA Design von University of Colorado Boulder

432 Bewertungen
122 Bewertungen

Über den Kurs

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....


6. Juni 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

4. Juni 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .

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101 - 123 von 123 Bewertungen für Hardware Description Languages for FPGA Design

von Muhammad Z Y

7. Apr. 2020

Course content is moderate. But also have complexity level higher for a beginner.

von Uzair A

9. Okt. 2020

its a very nice course. Its help me a lot to understand the basic of fpga.

von Apoorva S

25. Mai 2020

A very engaging course to do for beginners having fundamentals strong.

von Yuvraj S R

18. Mai 2020

Explanations are not that good for some circuits like memory

von Sourav N

18. Sep. 2020

There should have been more examples of problems.


30. Apr. 2020

a big thank you to all the professiors

von Engels M

3. Dez. 2021

Concise, practical and useful

von Prakash K R

24. Juni 2020

It should be more elaborative


7. Juni 2020


von J S

5. Aug. 2020


von Julien T

7. Dez. 2021

I​nteresting course but exercises shall be reworked as sometimes it's not clear what is the expected output so we end up guessing via the testbench. Another issue is that some half backed quizzes prevent you from practicing the exercises until you pass even though practicing is key to understand the concepts...

von Islam E

31. Mai 2020

this course need a person who knows before the basics of both VHDL/Verilog. because i know some basics of VHDL i understood its part but verilog was a little bit hard to me to understand it

von Harsh A

15. Juni 2020

Verilog part is explained very well but VHDL part completely unsatisfied.

von Sachin A

21. Apr. 2020

Very introductory. Verilog and VHDL exercises are copied.

von Sakshat R

28. Mai 2020

Innovative teaching, but very poor assignments

von Samuel C

14. Aug. 2020

A decent introduction to HDL.

von Pushkar A

30. Sep. 2020

Teaching could be better.


11. Juli 2021


von Rishi D

12. Juni 2020

teacher as well as way of teaching is not good . assignments are great though

von Ethan R

11. Apr. 2020

The highlight of this course was the recommended reading materials.

von Surabhi M

8. Nov. 2020

not clear.

von saikumar s

31. Okt. 2020

There is no technical support

von Muhammet M K

23. Aug. 2021