Chevron Left
Zurück zu Hardware Description Languages for FPGA Design

Kursteilnehmer-Bewertung und -Feedback für Hardware Description Languages for FPGA Design von University of Colorado Boulder

4.3
Sterne
399 Bewertungen
111 Bewertungen

Über den Kurs

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own....

Top-Bewertungen

JS
6. Juni 2021

I really liked this course . if someone wants to know how digital circuits are made inside of computer then this course could be proven as turning point in his way of learning .

KK
4. Juni 2020

This is very good course , but i found some little missing details related to reading materials .\n\nBut this was really very helpful course for me as fresher .

Filtern nach:

101 - 112 von 112 Bewertungen für Hardware Description Languages for FPGA Design

von Sakshat R

28. Mai 2020

Innovative teaching, but very poor assignments

von Samuel C

14. Aug. 2020

A decent introduction to HDL.

von Pushkar A

30. Sep. 2020

Teaching could be better.

von JYOTI S S

11. Juli 2021

good

von Damián E A

22. März 2021

Weeks 3 and 4 are the same as weeks 1 and 2, just in another (very similar) language. No many new topics compared to the first course of the specialization. Several weeks assignment are blocked by very tricky quizzes that can be taken only once every 72 hours, what makes it very difficult to accomplish everything in only 4 weeks.

von Eddy Z

12. Feb. 2021

Instruction is somewhat unclear. The instructors just read through example code but fail to adequately explain how the Verilog and VHDL languages actually work. I learned most of that from a separate textbook. Homework assignments' instructions are often lacking in specificity, forcing students to make assumptions.

von Claudio C

27. Juli 2021

The course is not bad but it is not good either. It is OK as an overview of vhdl/verilog but it is not by any means a university quality course. Not worth the price.

von Rishi D

12. Juni 2020

teacher as well as way of teaching is not good . assignments are great though

von Ethan R

11. Apr. 2020

The highlight of this course was the recommended reading materials.

von Surabhi M

8. Nov. 2020

not clear.

von Han L L

19. März 2021

THIS IS A SCAM!! Week2 Quiz failure resulting blocking on Readings page to get all the files you needed to do the rest of the assignment. And the quiz is only 1 attempt for 72 HOURS which means you will can't do anything for 3 days. And if you fail again, you will definitely miss the deadline!!

von saikumar s

31. Okt. 2020

There is no technical support